1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a repairable complementary metal oxide semiconductor field effect transistor (CMOSFET) and a method for fabricating the same.
2. Discussion of the Related Art
The metal oxide semiconductor (MOS) technique was developed before 1960. In the MOS technique, the surface of a semiconductor is processed with a silicon oxide film to provide a good insulation characteristic. This has improved the performance of transistors and the fabricating method thereof.
The MOS technique gave an impetus to the practical use of semiconductor surface devices, and the first field effect transistors (FETs) became known around 1962.
P channel MOS, N channel MOS, and complementary MOS (CMOS) are all MOSFET devices. When MOS devices started to be produced, PMOS devices were preferred due to its facility of adjusting power consumption and advantages in the processes in fabricating integrated circuits. The speed of MOS devices has become much more important and NMOS devices have become preferred because the mobility of carriers is two and a half times as fast as the mobility of holes. As for CMOS devices, their integration density is significantly lower and their fabricating process is quite complex in comparison with NMOS devices and PMOS devices. However, CMOS devices have very good power consumption. Currently, NMOS is utilized for the memory cells of a semiconductor device and CMOS for periphery circuits.
CMOS is classified into bulk CMOS and SOI (silicon on insulator) CMOS. In bulk CMOS, a semiconductor device is constructed from the inside of a semiconductor substrate. In SOI CMOS, a silicon single crystalline thin film is formed on a insulating layer and a semiconductor device is formed thereon. The SOI structure is advantageous because all capacitances and parasitic effects relating to the substrate can be ignored and CMOS circuits can be produced without latch-up or soft errors.
There are three types of SOI techniques. One of them is an epitaxial growth method in which a thin film of single crystal silicon is grown on a single crystalline insulating layer such as sapphire. Another technique is the deposition recrystallization method in which a polycrystalline or amorphous silicon thin film is deposited on an oxide insulating layer to be laterally melted and recrystallized or transformed into a solid phase epitaxy. The third method is a single crystallization division method in which an insulating layer such as an oxide layer is buried in a semiconductor substrate.
Silicon on sapphire (SOS) represents the epitaxial deposition method. In a melting recrystallization method, which belongs to the deposition recrystallization method, a portion of a polysilicon thin film deposited on an oxide layer by a chemical vapor deposition (CVD) process is heated by an energy beam, such as a laser beam or electron beam, and the melted portion of the polysilicon thin film is recrystallized on the wafer to form a single crystalline thin film. In the solid phase epitaxy method, amorphous silicon is deposited on crystallization areas of an insulating layer on a semiconductor substrate and then is annealed to be epitaxially grown. In the single crystallization division method, oxygen ions and nitrogen ions are implanted into a single crystalline silicon substrate so that an oxide layer or a nitride layer is buried in the substrate except the single crystalline silicon layer of a surface layer. In particular, the method of implanting oxygen ions is called separation by implanted oxygen (SIMOX) method.
As described above, the SOI structure has various advantages. In particular, an SOI CMOS is useful and advantageous because of good power consumption, high integration, low generation rate of soft errors, low generation of latchup, and high speed operation.
A conventional CMOSFET using an SOI structure and a method for fabricating the same will be discussed with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a conventional CMOSFET having a silicon on sapphire (SOS) structure. First, an n-type mesa silicon layer 3 and a p-type mesa silicon layer 4 are selectively formed on a sapphire substrate 1. A gate insulating layer 5 and a gate electrode 6 are successively formed on each of the n-type mesa and the p-type mesa silicon layers 3 and 4. N-type impurity regions 8 are formed in the p-type mesa silicon layer 4 at both sides of the gate electrode 6 and p-type impurity regions 7 are formed in the n-type mesa silicon layer 3 at both sides of the gate electrode 3. In this case, the n-type and p-type impurity regions 8 and 7 are all used as source and drain regions of a transistor.
FIGS. 2a to 2e are cross-sectional views showing the process steps of a method for fabricating the conventional CMOSFET of FIG. 1.
Referring initially to FIG. 2a, an n-type silicon layer 2 is formed on a sapphire substrate 1 using a general SOS structure.
Referring next to FIG. 2b, the silicon layer 2 is selectively patterned by a photolithography process and a photo etching process to form a pair of n-type mesa silicon layers. Subsequently, a photoresist film PR.sub.1 is coated on the entire surface of the substrate 1 including the pair of n-type mesa silicon layers and patterned to be removed on one of the pair of n-type mesa silicon layers. Next, p-type impurity ions are implanted into the exposed n-type mesa silicon layer so that the exposed n-type mesa silicon layer 4 becomes a p-type mesa silicon layer 4.
Referring to FIG. 2c, the remainder of photoresist film PR.sub.1 is removed. Another photoresist film PR.sub.2 is coated on the entire surface including the p-type and n-type mesa silicon layers 4 and 3 and then patterned by an exposure and development process so that the n-type mesa silicon layer 3 is exposed. N-type impurity ions are implanted into the exposed layer 3 for recrystallization of the n-type mesa silicon layer 3. At this time, the ions implanted are silicon ions.
Referring to FIG. 2d, after implanting the ions for recrystallization, n-type impurity ions for adjusting a threshold voltage of a transistor and n-type impurity ions for adjusting punch-through are implanted into the bulk of the n-type and p-type mesa silicon layers 3 and 4.
Referring to FIG. 2e, a gate insulating layer 5 and a gate electrode 6 are successively formed on the center of each of the n-type and p-type mesa silicon layers 3 and 4. Next, n-type and p-type impurity regions 8 and 7 are formed in the p-type and n-type mesa silicon layers, respectively, at both sides of the gate electrode 6. In this case, the n-type and p-type impurity regions 8 and 7 are used as source and drain regions.
However, the conventional CMOSFET and the method for fabricating the same have problems. First, since the bulk areas are where source and drain regions and channel regions are formed below a gate electrode in its construction, it is difficult to open a bias contact window with regard to the bulk areas. Further, because a bulk doping process for adjusting the threshold voltage that has important influence on device performance has to be performed in an early step, it is impossible to repair the device performance, thus decreasing the productivity and yield of CMOSFETs.